An embedded oscillator circuit often comprises a voltage reference, two capacitors charged by a current, one in each half-phase of the output clock, and two comparators which monitor at which time the voltage level on one of the capacitor nodes reaches the reference voltage. At that moment, the output clock is toggled and the other capacitor is charged. However, such embedded oscillator circuits usually suffer from output frequency variation, which may often prevent their use. Such output frequency variation may e.g. relate to variation between different semiconductor devices having embedded oscillator circuits that are designed to be substantially the same, but perform differently due to spread in their manufacturing, variation with temperature or variation over time. The variation may be present in the form of a temporary deviation or showing a long term frequency drift. While initial frequency offsets may be compensated by factory trim, frequency variation with temperature and frequency drift over time of usage may not be compensable by factory trim and may thus remain present. Such variations may be undesirable. Frequency tolerance requirements for some applications may already be too tight to be met with currently available embedded oscillator circuits, which may force a system designer to use external oscillators such as a quartz crystal oscillator.
FIG. 1 schematically shows an example of a prior art oscillator circuit 1P. The oscillator circuit 1P is arranged to provide an output clock signal CLK having an output frequency. The prior art oscillator circuit 1P will be described with further reference to FIG. 2. FIG. 2 schematically shows a time diagram the output clock signal CLK and voltages at nodes in the oscillator circuit. The oscillator circuit 1P comprises a voltage reference Vref, a first current source 11, a first capacitor 12, a first capacitor switch 13, a second current source 21, a second capacitor 22, a second capacitor switch 23, a first comparator 15P, a second comparator 25P and a flip-flop 30. The voltage reference Vref is provided from a reference current source 10 and a reference RC circuit 9 in a commonly known manner. The voltage reference Vref is arranged to carry a reference voltage. The symbol Vref will be used for the voltage reference as well as for the reference voltage in the further description. The first capacitor 12 is arranged to, by operation of the first capacitor switch 13, be chargeable by the first current source 11 to a first capacitor voltage Va on a first capacitor node 14 in a first half-phase P1 of the output clock cycle and to be dischargeable in a second half-phase P2 of the output clock cycle. The second capacitor 22 is arranged to, by operation of the second capacitor switch, be chargeable by the second current source to a second capacitor voltage Vb on a second capacitor node 24 in the second half-phase P2 of the output clock cycle and to be dischargeable in a first half-phase P1 of the output clock cycle. The first comparator 15P is arranged to provide a first comparator output 16 from continuously comparing the first capacitor voltage to the reference voltage. The second comparator 25 is arranged provide a second comparator output 26 from continuously comparing the second capacitor voltage to the reference voltage. The flip-flop being 30 is connected to the first comparator 15P and the second comparator 25P to receive the first comparator output 16 and the second comparator output 26 on its inputs and to generate the output clock signal CLK and an inverted output clock signal CLK* on its outputs. The flip-flop 30 is connected to the first comparator and the second comparator for operating the first capacitor switch 13 and the second capacitor switch 23 in dependency on respectively the output clock signal CLK and the inverted clock signal CLK*.